Charge recycling a 1 of n ndl gate with a time varying power supply

ABSTRACT

This disclosure describes a time varying power supply that may include a resonator circuit comprising an inductor having first and second terminals, a first capacitor coupled to the first terminal, and a second capacitor coupled to the second terminal, where the first capacitor produces a first time varying power supply output and wherein the second capacitor produces a second time varying power supply output. The time varying power supply may further include an exciter circuit comprising a first PFET and a first NFET coupled to the first terminal and a second PFET and a second NFET coupled to the second terminal. The first and second PFETs and the first and second NFETs may be coupled to a corresponding one of four non-overlapping clock phases.

PRIORITY CLAIM

This application is a continuation of U.S. patent application Ser. No.12/743,689, entitled “Charge Recycling a 1 of N NDL Gate with a TimeVarying Power Supply,” filed May 19 2010, which is a National Stageapplication of International Application number PCT/US08/83962, filedNov. 19, 2008, which claims priority to U.S. Provisional ApplicationSer. No. 60/989,009, filed Nov. 19, 2007, each of which is herebyincorporated by reference in its entirety as though fully and completelyset forth herein.

TECHNICAL FIELD

This disclosure relates to charge recycling with power supplies. Morespecifically, this disclosure relates to charge recycling a 1 of N NDLgate with a time varying power supply.

BACKGROUND ART

Charge recycling and adiabatic charging are two circuit technologiesthat can be employed to reduce the energy dissipated by an integratedcircuit. These techniques are particularly useful in charging anddischarging large capacitive loads or where the charging is performed ina cyclical fashion.

Conventional Charging

A large contribution to the total energy dissipated by an integratedcircuit is the result of the charging and discharging of capacitivesignal nodes within the circuit. This effect can be understood throughthe examination of a simple CMOS inverter as illustrated in FIG. 1.

Initially, the voltage across the capacitor 18 is zero and no energy isstored in the capacitor. The input signal 12 turns the P-channel MOSFET14 off, and turns the N-channel MOSFET 16 on which grounds capacitor 18.When it is time to charge the capacitor 18, the P-channel MOSFET 14conducts allowing current to flow from the power supply into thecapacitor 18. Once the P-channel MOSFET 14 is conducting, the circuitcan be modeled as a simple RC circuit 20 as illustrated in FIG. 2 whichshows a power supply 22 supplying power to resistor 24 and capacitor 26.The RC circuit has the value of the resistor 24 as the “on” resistanceof the MOSFET.

The energy dissipated in the circuit is the result of the current i(t)flowing through resistor 24 and is given by:

$\begin{matrix}{E_{diss} = {\int_{0}^{\infty}{{i^{2}(t)}R{t}}}} & (1)\end{matrix}$

The current flowing through the resistor 24 is the same as that flowingthrough the capacitor 26, which is given by:

$\begin{matrix}{{i(t)} = {C\frac{{V_{c}(t)}}{t}}} & (2)\end{matrix}$

Combining equations 1 and 2 and solving the resulting expression, it canbe seen that the energy dissipated in the resistance is ½CV². It isimportant to note that due to charging with a constant voltage, thedissipation through the resistor is independent of the value of theresistor.

The charge necessary to charge the capacitor to the supply potential isequal to CV. This implies a total energy removed from the power supplyis CV². However, the charge is delivered through the resistor R and, asindicated above, the energy dissipated through the resistor is ½CV².Thus, one half of the energy removed from the power supply is dissipatedin the resistor as heat, the other half going to charging the load.

When the load is discharged, i.e., the N-channel MOSFET conducts anddischarges the capacitor to ground, a similar phenomenon occurs andanother ½CV² is dissipated in the resistance of the N-channel MOSFET.

In the conventional case, both the charging and discharging of thesignal node capacitance results in a dissipation of ½CV². All of theenergy sourced from the power supply is eventually converted to heat inthe resistances.

Adiabatic Charging

In thermodynamics, when a process does not transfer heat to the workingfluid, it is referred to as being adiabatic. This concept can beextended into electronics and specifically into the charging of signalnodes within an integrated circuit. If a signal node can be charged ordischarged without dissipating energy in the resistance, then thecharging process is adiabatic.

To realize an adiabatic charging process, it is necessary to have moreprecise control of how the capacitive load is charged over time. Thiscan be achieved by using a time-varying power supply that starts at zeroand ramps over time towards the desired supply voltage as illustrated inFIG. 3. The linear voltage ramps provides a constant current and limitsthe voltage across the resistance to an arbitrarily small level. Theenergy dissipated in the resistor is given by:

$\begin{matrix}{E_{diss} = {\left( \frac{RC}{T} \right){CV}_{dd}^{2}}} & (3)\end{matrix}$

It is evident from equation 3 that the energy dissipated in the resistorfor this charging scenario is a function of the period of thetime-varying supply. Increasing the period results in less dissipatedenergy and, in the case where T>>RC, the dissipation approaches zero.With the use of a decreasing voltage ramp, the load capacitance can bedischarged in an adiabatic fashion which results in the same expressionfor the energy dissipated.

When adiabatic charging and discharging are used together, the reductionin dissipated energy can be dramatic. Referring to FIG. 4, consider thecase of a capacitive load in circuit 40 that has been discharged toground at time t₀. For the example, it is assumed that the voltagesource 42 is like an energy reservoir 41 storing CV² of energy and thecapacitor 46 is like an empty energy reservoir 48 with the circuit 40having the resistor 44.

In FIG. 5, When the capacitive load is charged, 1/2CV² is delivered tothe energy reservoir 58 that is the capacitor 56. Another RC/TCV² hasbeen removed from the power supply reservoir 51 and dissipated as heatin resistor 54 in accordance with equation 3. Thus, a total of(½+RC/T)CV² is removed from the power supply reservoir 51 contrastedwith the conventional charging case where the entire supply reservoir isemptied. When the load is discharged, another RC/TCV² is dissipated inresistor 54 as the energy is returned to the supply reservoir 51 leavinga total of CV²−2RC/TCV² in the supply 51 compared to the case ofconventional charging where the supply reservoir is completely drained.In the limiting case where T>>RC, the circuit dissipates no energy inthe resistor, and the charge drawn from the power supply to charge thecapacitor is returned to the power supply when the capacitor isdischarged.

Ordinary power supplies are incapable of dealing with the chargereturned during an adiabatic discharge as it is usually dissipated toground through a shunt impedance. This limitation renders the adiabaticdischarging process no more efficient than the conventional dischargingmethod. In order to take advantage of the of the returned energy, it isnecessary to use a resonant source for the time-varying power supply asit is capable of reclaiming the returned charge, storing it, and makingit available for use in subsequent clock cycles.

SUMMARY

This disclosure describes a circuit that is a basic charge recyclinggate 70 that comprises a precharge node 75; an output charging network78 that couples to a signal output 72; an output pre-charge and nullpropagate network 77; an evaluation network 76 with a signal input 71that couples to the precharge node 75 and to the output charging network78 and the output precharge and null propagate network 77; a first timevarying power supply TVS0 that couples to the precharge node 75 and theoutput charging network 78; a second time varying power supply TVS2 thatcouples to the evaluation network 76; and a keeper circuit 79 thatcouples to the signal output 72 and the evaluation network 76.

Additionally, this disclosure describes a circuit that is a time varyingpower supply 130 that includes a resonator circuit 131, an amplitude andpower check circuit 135, one or more overshoot and an undershoot voltageclamps 1105 and 112, exciter circuits 137 and 136, and current monitorcircuits 138 and 139. In addition, the circuit includes frequency selftuning with the amplitude and power check circuit 135, capacitor banks132 and 134, and the inductor tap select controller 133. Amplitude selftuning is provided by the amplitude sample and compare circuit 144.Further, a phase shift control circuitry 150 is also provided. And,distributed control switching circuitry 160 for power management is alsoprovided.

BRIEF DESCRIPTION OF DRAWINGS

To further aid in understanding the disclosure, the attached drawingshelp illustrate specific features and the following is a briefdescription of the attached drawings:

FIG. 1 illustrates a simple CMOS inverter.

FIG. 2 illustrates the electrical modeling of a simple RC circuit.

FIG. 3 illustrates the voltage over time of a time varying power supply.

FIG. 4 illustrates the initial circuit state of an electrical model ofthe time varying power supply.

FIG. 5 illustrates the circuit state of the time varying power supplyafter the capacitor is charged.

FIG. 6 illustrates an exemplary 1 of N NDL gate.

FIG. 7 discloses an embodiment of the basic charge recycling NDL gate.

FIG. 8 illustrates a simple inductive circuit.

FIG. 9 illustrates the extension of a simple LC circuit to four phases.

FIG. 10 illustrates an embodiment of the individually clocked 2N2P LCexciter circuit.

FIG. 11 discloses an embodiment of the exciter circuit with overshootand undershoot voltage clamps.

FIG. 12 discloses an embodiment of the time varying power supply withcapacitor banks for frequency self tuning.

FIG. 13 discloses an embodiment of the time varying power supply withadjustable inductance.

FIG. 14 discloses an embodiment of the time varying power supply withamplitude self tuning.

FIG. 15 discloses a phase shifting system for an embodiment of the timevarying power supply.

FIG. 16 discloses of an embodiment of the time varying power supplyusing distributed control switches.

DETAILED DESCRIPTION

This disclosure describes a method and apparatus for charge recycling a1 of N NDL gate with a time varying power supply. This disclosuredescribes numerous specific details in order to provide a thoroughunderstanding of the present disclosure. One skilled in the art willappreciate that one may practice aspects of the present disclosurewithout these specific details. Additionally, to facilitate exposition,this disclosure does not describe some well known items in detail.

The Basic Charge Recycling NDL Gate

In order to take advantage of the adiabatic charging and dischargingprocesses described above, two circuit technologies are necessary. Thefirst of these technologies is the logic gate itself.

Several different logic families have been developed to enable thecharging and discharging processes described above. Each of thesefamilies have drawbacks ranging from requiring complete differentiallogic to low noise margin. A new logic family derived from a 1-of-N NDLtopology solves these concerns and provides a robust circuit solution.The 1 of N NDL topology is Intrinsity Inc.'s proprietary FAST14® 1-of-NDomino Logic (NDL®) circuit technology. FAST14® and NDL® are registeredtrademarks of Intrinsity, Inc. FAST14 Technology and NDL gates arebetter described in U.S. Pat. Nos. 6,069,497 and 6,118,304, both ofwhich are incorporated by reference for all purposes into thisspecification.

Referring to FIG. 6, a 1-of-N NDL gate 60 is an ideal starting point forcreating a charge recycling logic family. Gate 60 comprises apre-charged node, i.e., the top-of-stack, that is discharged through theevaluation network 66 if the logical state of the inputs 61 is correct.The value of the top-of-stack node is output to other gates throughinverter 68.

P-channel MOSFET 64 is responsible for the pre-charge of thetop-of-stack node. When CLK 63 is low, PFET 64 conducts and charges thetop-of-stack to the supply voltage. When CLK goes high, PFET 64 isturned off and the gate 60 begins to evaluate.

During evaluation, N Channel MOSFET 65 conducts and, depending on thestate of the inputs, the top-of-stack node discharges to ground. Theevaluation network 66 comprises various combinations of N-channelMOSFETs coupled together to implement a given logic function based onthe 1-of-N encoded data inputs.

As with all dynamic logic circuits, there is a risk of unintendeddischarge of the top-of-stack node due to spurious noise on one or morethe inputs. To combat this, a full keeper (which is inverter 68 andinverter 67 combined) is used. By supplying a small amount of additionalcharge, the additional inverter 67 assists in keeping the top-of-stackvoltage at the power supply level during noise, charge sharing, andundesirable coupling into the node. The inverter is sized to besufficiently weak so that during a desired top-of-stack discharge, theevaluate stack has no difficulty overcoming the keeper inverter.

Several key changes are required to a basic NDL gate to allow it to beused in a charge recycling system. The first of these changes involvesthe output inverter 68 of FIG. 6. Referring now to FIG. 7 that disclosesa basic charge recycling NDL gate 70, the output inverter has beenreplaced by two networks that control the charging and discharging ofthe data output. The first network, output charging network 78, connectsthe output 72 to the first time-varying power supply TVS0 when the gate70 evaluates, i.e., the top-of-stack discharges, to adiabatically chargethe output. As the first time varying supply begins its low goingtransition, the output charging network 78 continues the connection tothe output 72 allowing the output to discharge in an adiabatic fashion.One skilled in the art will appreciate that output charging network 78may comprise appropriate circuitry to accomplish its task.

The second network, output pre-charge and null propagate network 77,ensures a solid ground level on the output 72 during pre-charge andmaintains an active connection should the gate not evaluate (Nullpropagate). Null value propagation is better described in U.S. Pat. No.7,053,664, which is incorporated by reference for all purposes into thisspecification. One skilled in the art will appreciate that outputpre-charge and null propagate network 77 may comprise appropriatecircuitry to accomplish its task.

A similar technique is employed to discharge the top-of-stack node in anadiabatic fashion. The evaluate device 65 of gate 60 has been removedand the bottom of the evaluation network has been connected directly toa second time-varying power supply TVS2. Assuming the input data 71 issuch that gate 70 will evaluate, as time-varying power supply TVS2transitions to a low state, the top-of-stack node will follow,approximating an adiabatic discharge which limits the dissipationthrough the MOSFETs in the evaluation stack. As time-varying powersupply TVS2 transitions to a high state, the top-of-stack node ischarged in an adiabatic fashion up to V_(dd)-V_(th.) PFET 75 finishesthe pre-charge of the top-of-stack.

Finally, by connecting PFET 75 to one of the time varying powersupplies, the gate capacitance of the FET is charged and discharged inan adiabatic fashion thus reducing dissipation and allowing for morecharge recycling.

It is also important to note that inverter 79 is still present in thecharge recycling version of the NDL gate. This maintains similar noiseimmunity characteristics to the conventional style gate.

The charge recycling version of the NDL gate maintains the same basictopology but, as described above, allows both the top-of-stackcapacitance and the output load capacitance to be charged and dischargedin a fashion that approximates the adiabatic ideal. As such, this gatedissipates less energy than its conventional counterpart and allows fora portion of the energy stored in the aforementioned capacitances to berecycled reducing the overall power consumption.

The Time-Varying Power Supply

The second crucial circuit technology to realize the benefits of theadiabatic charging and discharging is the time varying power supply. Aspreviously indicated, a power supply that varies in time is necessary tocontrol the charging and discharging of signal nodes in an adiabaticfashion. Furthermore, the time varying power supply must allow for thereclamation (recycling) of the charge returned during the adiabaticdischarge process. During the charging portion of the cycle, the timevarying power supply sources the necessary energy to charge the load.When the load is discharged, the time varying power supply functions asa energy sink, reclaiming that energy from the load not dissipated asheat in the circuit's resistances and storing it for use during the nextcharging cycle.

A resonant circuit comprising an inductor and the aggregate on-chipcapacitance is the best choice for generating the necessary time varyingpower supplies. The use of inductance will generate voltage waveformsthat are sinusoidal. While this is not the ideal linear voltage rampdescribed above, it serves as a close approximation. Finally, care mustbe given in the resonator circuitry to minimize dissipation and allowfor phase locking to the master time reference.

The Resonator

One technique to create a power supply capable of recycling the energysaved in the adiabatic charging process involves the use of an inductor.Referring now to FIG. 8, the idea is to create a resonant circuitcomprising the inductor 81 (either internal or external to the chip) andthe on-chip capacitance 82 (with or without on or off chip ballastcapacitance). The resonant frequency of the circuit is given by:

$\begin{matrix}{\omega_{0} = \frac{1}{\sqrt{LC}}} & (4)\end{matrix}$

If the inductor value is chosen such that the circuit resonates at thedesired clock frequency, little energy is required to keep the circuitoperating. Furthermore, the energy stored in the electric field of thecapacitor can be transferred (less dissipation) to the magnetic field ofthe inductor during the adiabatic discharge process, thus enablingcharge recycling.

The simple LC circuit above can be extended to provide the four phasesnecessary for the operation of the aforementioned recycling NDL gates.Referring now to FIG. 9 and circuit 90, the addition of a secondinductor and a division of the capacitive load into four equalcomponents accomplishes this task. Each of the two separate tankcircuits creates (91, 92, 93 and 94, 95, 96) two clock phases 180° outof phase with each other. The excitation circuitry for the tanks can beused to induce the necessary 90° phase shift between the two tankcircuits thus creating the required four clock phases.

Referring now to FIG. 10, the excitation circuit that is the best forchoice for the recycling NDL gate is the individually-clocked 2N2Parrangement. The resonator circuit 104 comprises inductor 103,capacitors 1001 and 1002, which produces a first time varying powersupply TVS0 and a second time varying power supply TVS2. PFET 108 andNFET 105 form a first excitation circuit 101 for CLKA and CLKBX, andPFET 106 and NFET 107 form a second excitation circuit 102 for CLKB andCLKAX.

In this circuit 100, the individual transistors (104, 105, 106, 107) areactivated with non-overlapping clock pulses derived from the master timereference. By using such pulses, it is possible to individually controlthe time each transistor is activated thus allowing for the circuit tobe “tuned” to provide the minimum amount of energy necessary to excitethe tank into resonance. The pulse driven arrangement also minimizesshoot-through current common in these types of structures by ensuringthat a PFET and a NFET on the same side of the inductor are not on atthe same time, e.g., 104-105 and 106-107.

Since the overall system requires four clock phases (CLKA, CLKAX, CLKB,CLKBX), two excitation circuits are required, one each connected acrossthe inductor. Capacitors 1001 and 1002 could either be discretecapacitors or they could be the capacitance associated with TVS0 orTVS2.

Overshoot and Undershoot Clamps

When inductors are employed in electric circuits, care must be taken toensure that large voltages are not developed. At resonance, the voltagegain of a RLC circuit can be significant and generate voltages in excessof the power supplies, i.e., voltages above VDD and below ground.

Such excursions beyond the power supply range can stress or damage thecircuits on the chip. For example, voltages larger than the recommendedsupply voltage can damage the gate oxide of a MOSFET rendering thedevice inoperable. It is also possible to forward bias the intrinsicdiodes formed at the source and drain regions of MOSFETs. When thishappens, carriers are injected into the substrate and, if the carriersare sufficient in quantity, trigger the effect known as latch-up.

To prevent the excursions from initiating undesirable effects, voltageclamps can be added as illustrated in FIG. 11 with circuit 110. Circuit110 comprises a resonator circuit 111 with exciter circuits 1107 and1106. Resonator circuit 111 comprises inductor 1103 and capacitors 1102and 1104 and produces the first time varying power supply TVS0 and thesecond time varying power supply TVS2. Excitation circuit 1107 comprisesPFET 114 and NFET 113 with CLKA and CLKBX; while excitation circuit 1106comprises PFET 115 and NFET 116 with CLKB and CLKAX.

In this circuit, first clamp circuit 1105 and second clamp circuit 112are implemented as diode-connected MOSFETs. The first clamp circuit 1105comprises PFET 117 and NFET 119; while the second clamp circuit 112comprises PFET 118 and NFET 1101. In operation, if TVS0 attempts to goabove the supply voltage VDD, PFET 117 will activate and the excessenergy in the tank will be shunted into the positive power supply. Asimilar effect happens if TVS0 swings below ground where NFET 119 willactivate to hold the time-varying supply at ground. The second clampcircuit 112 with PFET 118 and NFET 1101 performs the same functions forTVS2.

While the clamps shown are implemented as diode-connected MOSFETs, anystructure that allows for a connection between the time varying suppliesand the power supplies when the time varying supplies move beyond thesupply voltages would be acceptable. For example, the diode-connectedMOSFETs could be replaced by explicit PN diodes. In addition, oneskilled in the art will appreciate that the clamp circuits can beincorporated into the excitation circuits.

Frequency Self-Tuning

The charge recycling NDL system provides maximum power reduction whenthe LC tank circuit that comprises an explicit inductor and theaggregate capacitance of the time varying power supply nodes is drivenat its resonant frequency. During the design process, the totalcapacitance is estimated from the mask data and the inductor valuechosen to achieve resonance at the desired clock frequency. However,variations in the manufacturing process can result in a differentcapacitance than what was estimated and which will cause the resonantfrequency of the circuit to be at a different frequency than desired. Amechanism is needed that allows the LC tank circuit to be re-tuned tothe proper frequency post-fabrication.

In the event that actual capacitance is less than what was anticipated,additional capacitance can be added as illustrated in FIG. 12 in smallincrements until the tank circuit resonates at the desired frequency.The circuit 120 comprises a resonator circuit 123 with time varyingpower supply nodes TVS0 and TVS2. As previously described in FIGS. 10and 11, exciter circuits 129 and 127 are coupled to the resonatorcircuit 123. And as previously described, one skilled in the art willappreciate that clamp circuits as described above may be incorporatedinto the exciter circuits.

Circuit 120 also comprises current monitor circuits 1201 and 128. Oneskilled in the art will appreciate that these circuits may compriseappropriate circuitry to limit the current flowing into and out ofresonator 123.

To determine if resonator circuit 123 is resonating, both the amplitudeof the time varying power supplies and the current being drawn by theexciter circuits need to be monitored. As resonator circuit 123approaches resonance, the amplitude of the time varying power supplieswill be at their largest value and the current sourced to the resonatorcircuit by the exciter circuits will be at a minimum. If this is not thesituation, the amplitude and power check circuit 126 can connectadditional capacitance into the time varying power supply nodes untilresonance is achieved such as illustrated by capacitor banks 124 and125. Although the topology shown is for the case where additionalcapacitance is required, it is also possible to connect additionalcapacitors in series with the time varying power supply nodes therebydecreasing the total capacitance. In addition, one skilled in the artwill appreciate that the amplitude and power check circuit 126 maycomprise appropriate circuitry to control and monitor the amplitude andpower of the time varying power supply nodes.

Assuming that the inductor of the resonator circuit is fabricated on thechip, it is also possible to re-tune the resonator circuit by changingthe value of the inductor as is illustrated in FIG. 13.

Circuit 130 comprises a resonator circuit 131 with time varying powersupply nodes TVS0 and TVS2. As previously described, exciter circuits136 and 137 are coupled to resonator circuit 131. One skilled in the artwill appreciate that clamp circuits as described above may beincorporated into the exciter circuits. Circuit 130 also comprisescurrent monitor circuits 138 and 139. And as previously illustrated,circuit 130 additionally comprises capacitor banks 132 and 134 withamplitude and power check circuit 135.

The inductor of the resonator circuit 131 can be tapped at one or morelocations within the spiral allowing several different values ofinductance from a single fabricated inductor and controlled by inductortap select controller 133. The amplitude and power check circuit 135generates signals to control the inductor tap select circuit 133. Basedon the value of the control signals, a different tap is selected as thesecond terminal of the inductor, thus varying the value of theinductance in the circuit and changing the resonant frequency. Theprocedure is repeated until resonance at the desired clock frequency isachieved. One skilled in the art will appreciate that tap select circuit133 may comprise appropriate circuitry to adjust the inductance ofresonator circuit 131.

It is also possible to combine both of the previous two methods so thatthe circuit's resonant frequency can be altered by adjusting either orboth the capacitance and/or inductance of the circuit.

Amplitude Self-Tuning

One of the challenges presented with the use of time varying powersupplies is the consequences of clock gating. In a traditional design,the clock connected to unused portions of circuitry is stopped, thussaving power by eliminating switching in the aforementioned unusedcircuits. When the circuit is needed, the clock is re-activated allowingthe circuit block to perform its designated function. With time varyingpower supplies, however, the situation is more complicated.

When a time varying power supply is disconnected from an unused circuitblock, a portion of the capacitive load that forms the resonant circuitis also disconnected. The removal of capacitance causes a shift in theresonant frequency of the system as well as an increase in the amplitudeof the power clocks. In order to realize a power savings associated withdisconnecting the unused circuit block, it is necessary to adjust theamplitude of the time varying power supplies so that less energy isadded to the system.

Referring now to FIG. 14, a feedback mechanism is employed in order toregulate the amplitude of the time varying power supplies. In this case,each time varying power supply is sampled near the terminals of theinductor. Circuit 140 comprises resonator circuit 142 with time varyingpower supplies TVS0 and TVS2. Coupled to resonator circuit 142 areexciter circuits 145 and 146 and amplitude sample and compare circuit144. The sampled peaks of the time varying power supplies TVS0 and TVS2are compared against the supply voltage and ground and a control signalis adjusted accordingly by amplitude sample and compare circuit 144. Ifthe amplitudes of the time varying power supplies are too low, thecontrol signal is adjusted such that the two exciter circuits supplyextra energy to the resonator circuit. If the amplitudes of the timevarying power supplies are too large, i.e., the peak-to-peak voltage islarger than the power supply voltage, then the control signal isadjusted such that the exciter circuits supply less energy too thecircuit. The natural dissipation within the resonator circuit is reliedupon to remove the excess energy and reduce the amplitude of the timevarying power supplies.

The method by which the exciter circuit supplies more or less energy canbe realized in two fashions. The first method, relies on an analog basedcontrol signal from amplitude sample and compare circuit 144. The analogsignal controls the bias point of the drive MOSFETs within the excitercircuits, effectively making the MOSFETs stronger or weaker as needed.The second method relies on a digital control signal composed of one ormore bits. The digital word encoded in the control signal is used toactivate or deactivate portions of a collection of MOSFETs that comprisethe drive devices within the exciter circuits. As the value of thedigital word changes, different numbers of MOSFETs are made active, thuschanging the effective size of the drive device thereby changing theamount of energy applied to the circuit.

Another method by which the power savings of clock gating can berealized involves the use of additional ballast capacitance. When aportion of the capacitive load is disengaged, it can be replaced byadditional ballast (balanced on both sides of the inductor). This willmaintain the proper resonant frequency and remove the need for adjustingthe exciter circuits as the time varying power supplies will maintaintheir desired amplitude. Since the ballast capacitance will be connecteddirectly to a time varying power supply, it will be charged anddischarged in an adiabatic fashion resulting in a power savings fromwhere the full load is connected (the charging and discharging of thecircuit loading is only partially adiabatic).

Phase Shift Control

In conventional NDL, controlling the phase relationship between thevarious clocks can be desirable. Clock phases 0 and 2 are generally 180°out of phase. This is the same for clock phases 1 and 3. At FMAX, anapproximate 90° phase shift is desired between the two groups of clocksphases which is generally accomplished using a fixed delay circuit.

The phase relationships for the time-varying supplies in the chargerecovery NDL implementation are similar. The 180° phase shift betweenphases 0 (1) and 2 (3) remains the same. Generally, FMAX is achievedwhen the overlap of even and odd phases are maximized. Therefore, aprecise 90° phase shift between phases 0 and 1 (2 and 3) is desirable.

The 180° phase shift between phases 0 and 2 (1 and 3) is inherent in theuse of the inductor to create the time-varying supplies. The reactanceof the inductor provides an exact 180° phase shift between its twoterminals when used in this fashion. With the use of two inductors, the180° phase relationship between phases 0 and 2 (1 and 3) is achieved.

In order to ensure the desired 90° phase shift between the two groups oftime varying power supplies, a system that samples the time varyingpower supplies, compares their relative phases and adjust the controlclock delay is employed as is illustrated in FIG. 15 and circuit 150.Circuit 150 comprises resonator circuit 152 with time varying powersupply nodes TVS0 and TVS2 and resonator circuit 159 with time varyingpower supply nodes TVS1 and TVS3. For simplicity, the resonator circuitsdo not show additional circuitry as previously discussed and includesthe exciter circuits, clamping circuits, current monitor circuits,capacitor banks, amplitude and power check circuits, inductor tap selectcontroller circuits, and amplitude sample and compare circuits.

The phase 0 time varying power supply TVS0 is sampled and converted to adigital signal by Time Varying Supply to Digital Converter circuit 155so that the phase comparison can more easily accomplished. The same isdone for the phase 1 time varying power supply TVS1 by Time VaryingSupply to Digital Converter circuit 158. One skilled in the art willappreciate that TVS2 and TVS3 may be used as well. Additionally, oneskilled in the art will appreciate that appropriate circuitry maycomprise the time varying supply to digital converter circuits toachieve their tasks.

Once the time varying power supplies signals have been converted todigital signals, the relative phase difference between the two phases isdetermined by the phase check circuit 156. In the ideal circumstance,the difference between the two signals is 90° and no action is taken.If, however, the phase difference between phases 0 and 1 is larger thanthe desired 90°, then the amount of delay in the adjustable delaycircuit 157 is reduce. Additional delay is added in the adjustable delaycircuit 157 should the phase difference between the two signals besmaller than the specified 90°. One skilled in the art will appreciatethat appropriate circuitry may comprise the phase check circuit and theadjustable delay circuit to achieve their tasks.

The system continuously adjusts the delay of control clock signal 1501for the phase 1-3 resonator circuit 159 relative to the control clocksignal 151 of resonator circuit 152 to maintain the desired phaserelationship between the two phase groups. With this type of system,variations due to process, supply voltage, and temperature can becompensated for allowing the desired phase relationships.

Distributed Control Switches

As a method to save power, a technique called clock gating is oftenemployed. This method disengages the clock from unused circuit blocks sothat the circuits within the block do not needlessly switch and consumepower. A similar technique can be employed with the charge recycling NDLlogic circuits as illustrated in FIG. 16 with circuit 160. Circuit 160comprises resonator 165 with time varying power supply nodes TVS0 andTVS2 and resonator 166 with time varying power supply nodes TVS1 andTVS3. For simplicity, the resonator circuits do not show additionalcircuitry as previously discussed and includes the exciter circuits,clamping circuits, current monitor circuits, capacitor banks, amplitudeand power check circuits, inductor tap select controller circuits,amplitude sample and compare circuits, and phase delay circuitry.

Coupled to resonator circuits 165 and 166 are one or more switches 169,168, through the Nth switch 167 (any number of switches). Each switch iscontrolled by its own control signal 1604 for switch 169, 1605 forswitch 168, and the Nth control signal 161 for the Nth switch 167.Coupled to the switches are one or more NDL circuit blocks 1603, 1602,through the Nth circuit block 1601 (any number of NDL circuit blocks).One skilled in the art will appreciate that appropriate circuitry maycomprise the switch circuits to achieve its task. Additionally, oneskilled in the art will appreciate that the NDL circuit blocks maycomprise a variety of NDL circuits that perform various tasks.

When the switches are closed, the time varying power supplies are passedon directly to the internal circuits within the appropriate NDL circuitblocks. If the system determines that one or more NDL circuit blocks arenot needed for a period of time, the appropriate switch control signalsare transitioned. The change in state of the switch control signalsdisconnects the internal circuits in the target NDL circuit block fromthe time varying power supplies and drives the local supply nodes to aknown state to prevent odd behavior in the circuit and allow for easierstartup when the block is needed.

In addition, the switches may comprise additional circuitry to provideadditional clocks or signals such as illustrated by signals 1606-1608 toaid in testing, debug, alternate power supplies, etc. One skilled in theart will appreciate that the switch control signals will have to besupplemented with additional information to select which alternativeclock will be connected to the intended circuit blocks.

To summarize, this disclosure describes a circuit that is a basic chargerecycling gate 70 that comprises a precharge node 75; an output chargingnetwork 78 that couples to a signal output 72; an output pre-charge andnull propagate network 77; an evaluation network 76 with a signal input71 that couples to the precharge node 75 and to the output chargingnetwork 78 and the output precharge and null propagate network 77; afirst time varying power supply TVS0 that couples to the precharge node75 and the output charging network 78; a second time varying powersupply TVS2 that couples to the evaluation network 76; and a keepercircuit 79 that couples to the signal output 72 and the evaluationnetwork 76.

Additionally, this disclosure describes a circuit that is a time varyingpower supply 130 that includes a resonator circuit 131, an amplitude andpower check circuit 135, one or more overshoot and an undershoot voltageclamps 1105 and 112, exciter circuits 137 and 136, and current monitorcircuits 138 and 139. In addition, the circuit includes frequency selftuning with the amplitude and power check circuit 135, capacitor banks132 and 134, and the inductor tap select controller 133. Amplitude selftuning is provided by the amplitude sample and compare circuit 144.Further, a phase shift control circuitry 150 is also provided. And,distributed control switching circuitry 160 for power management is alsoprovided.

Other embodiments will be apparent to those skilled in the art afterconsidering this disclosure. The specification and embodiments discussedabove are merely examples, with the scope of the present disclosurebeing determined by the following claims.

What is claimed is:
 1. A time varying power supply, comprising: aresonator circuit comprising an inductor having first and secondterminals, a first capacitor coupled to the first terminal, and a secondcapacitor coupled to the second terminal, wherein the first capacitorproduces a first time varying power supply output and wherein the secondcapacitor produces a second time varying power supply output; and anexciter circuit comprising a first PFET and a first NFET coupled to thefirst terminal and a second PFET and a second NFET coupled to the secondterminal, wherein each of the first and second PFETs and the first andsecond NFETs is coupled to a corresponding one of four non-overlappingclock phases.
 2. The time varying power supply of claim 1, furthercomprising an amplitude self tuning circuit coupled to the excitercircuit, wherein in response to detecting that the amplitude of thefirst and second time varying power supply outputs are lower than aground voltage, the amplitude self tuning circuit adjusts the excitercircuit to increase energy supplied by the exciter circuit, and whereinin response to detecting that the amplitude of the first and second timevarying power supply outputs are higher than a supply voltage, theamplitude self tuning circuit adjusts the exciter circuit to decreaseenergy supplied by the exciter circuit.
 3. The time varying power supplyof claim 1, further comprising an overshoot voltage and undershootvoltage clamp circuit, wherein the overshoot voltage and undershootvoltage clamp circuit comprises a first device coupled to a positivepower supply and a second device coupled to a ground terminal, whereinin response to detecting that the resonator circuit is attempting to goabove a positive power supply voltage, the first device activates andshunts the resonator circuit to the positive power supply, and whereinin response to detecting that the resonator circuit is attempting to gobelow a ground voltage, the second device activates and shunts theresonator circuit to the ground terminal.
 4. The time varying powersupply of claim 1, further comprising an amplitude and power checkcircuit, wherein in response to detecting that the resonator circuit isnot at resonance during operation of the time varying power supply, theamplitude and power check circuit connects additional capacitance from acapacitor bank to the resonator circuit until resonance is achieved. 5.The time varying power supply of claim 4, wherein the resonator circuitcomprises an inductor having multiple tap locations, and wherein theamplitude and power check circuit further selects a different one of thetap locations until resonance is achieved.
 6. The time varying powersupply of claim 1, wherein the resonator circuit produces multiple timevarying power supply outputs having relative phase differences, andwherein a phase shift control circuitry adjusts the relative phasedifferences during operation of the time varying power supply.
 7. Thetime varying power supply of claim 1, further comprising: an overshootvoltage and undershoot voltage clamp circuit that couples to saidresonator circuit; an amplitude self tuning circuit coupled to saidresonator circuit; a phase shift control circuitry that couples to saidresonator circuit; and a distributed control switching circuitry thatcouples to said resonator circuit; wherein the frequency self tuningcircuit further comprises an inductor tap select controller circuit. 9.A system, comprising: a time varying power supply; and one or morecharge recycling gates coupled to the time varying power supply; whereinthe time varying power supply comprises: a resonator circuit comprisingan inductor having first and second terminals, a first capacitor coupledto the first terminal, and a second capacitor coupled to the secondterminal, wherein the first capacitor produces a first time varyingpower supply output and wherein the second capacitor produces a secondtime varying power supply output; and an exciter circuit comprising afirst PFET and a first NFET coupled to the first terminal and a secondPFET and a second NFET coupled to the second terminal, wherein each ofthe first and second PFETs and the first and second NFETs is coupled toa corresponding one of four non-overlapping clock phases.
 10. The systemof claim 9, wherein a given one of the one or more charge recyclinggates comprises: an output charging network that couples to a signaloutput and connects the signal output to the time varying power supplyduring evaluation of the given charge recycling gate to adiabaticallycharge and discharge the signal output; an output pre-charge and nullpropagate network that couples to said signal output and maintains aground level of the signal output during precharge of the chargerecycling gate; and a keeper circuit that couples to said signal output.11. The system of claim 9, wherein a given one of the one or more chargerecycling gates comprises: a precharge node; and an evaluation networkcoupled to a signal input and to said precharge node, and furthercoupled to the time varying power supply; wherein when the signal inputcauses the evaluation network to evaluate, the evaluation networkcouples the second time varying power supply input to adiabaticallycharge and discharge the precharge node.
 12. The system of claim 11,wherein the charge recycling gate further comprises a PFET controlled bythe time varying power supply, wherein the PFET is coupled to charge theprecharge node.
 13. The system of claim 9, wherein the charge recyclinggate comprises: a precharge node; an output charging network thatcouples to a signal output; an output pre-charge and null propagatenetwork that couples to said signal output; and an evaluation networkwith a signal input that couples to said precharge node and to saidoutput charging network and said output precharge and null propagatenetwork.
 14. The system of claim 13, wherein the charge recycling gatefurther comprises: a first time varying power supply input coupled tothe time varying power supply, wherein the first time varying powersupply input couples to said precharge node and said output chargingnetwork; a second time varying power supply input coupled to the timevarying power supply, wherein the second time varying power supply inputcouples to said evaluation network; and a keeper circuit that couples tosaid signal output and said evaluation network.
 15. The system of claim9, wherein the time varying power supply is included within a pluralityof time varying power supplies, wherein the time varying power suppliesare configured to produce time varying power supply outputs, and whereinthe system further comprises one or more switches, each coupled toreceive the time varying power supply outputs from the time varyingpower supplies and further coupled to one or more charge recyclingcircuits; and wherein each of the one or more switches is controlled bya respective control signal such that when a given switch is closed, thetime varying power supply outputs coupled to the given switch are passedto the one or more charge recycling circuits coupled to the givenswitch.
 16. The system of claim 15, wherein each of the one or moreswitches is further controlled by the respective control signal suchthat when the one or more charge recycling circuits coupled to the givenswitch are not needed for a period of time, the given switch disconnectsthe time varying power supply outputs from the one or more chargerecycling circuits coupled to the given switch.
 17. A method,comprising: generating a first and a second time varying power supplyoutput from a resonator circuit controlled by an exciter circuit;detecting that the amplitude of the first and second time varying powersupply outputs are either lower than a ground voltage or higher than asupply voltage; and in response to detecting that the amplitude of thefirst and second time varying power supply outputs are either lower thana ground voltage or higher than a supply voltage, adjusting the excitercircuit to vary the energy supplied by the exciter circuit to theresonator circuit.
 18. The method of claim 17, further comprising:detecting that the resonator circuit is attempting to go above thesupply voltage and responsively shunting the resonator circuit to apositive power supply.
 19. The method of claim 17, further comprising:detecting that the resonator circuit is attempting to go below theground voltage and responsively shunting the resonator circuit to aground terminal.
 20. The method of claim 17, further comprising:detecting that the resonator circuit is not at resonance andresponsively connecting additional capacitance from a capacitor bank tothe resonator circuit until resonance is achieved.